KVM: riscv: Fix NACL hfence entry update order
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
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| Linux | Linux | unaffected |
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| Linux | Linux | affected |
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No data.
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| Linux | Linux Kernel |
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| Linux | Linux Kernel |
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| Source | ID | Title |
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Ubuntu USN |
USN-9019-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-9020-1 | Linux kernel vulnerabilities |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.166% probability within 30 days)
Key SSVC decision points have not yet been added.
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| Metrics |
threat_severity
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cvssV3_1
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| Weaknesses | CWE-362 |
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| Description | In the Linux kernel, the following vulnerability has been resolved: KVM: riscv: Fix NACL hfence entry update order The SBI v3.0 specification (section 15.1.2) requires a nested HFENCE entry to be populated as follows: 1) find an unused entry with Config.Pending == 0 2) update the Page_Number and Page_Count words 3) update the Config word with Config.Pending set __kvm_riscv_nacl_hfence() writes the Config word first, so the SBI implementation (or NACL hardware) can observe a pending entry with pnum/pcount values left over from the previous use of that entry, resulting in incorrect TLB flush ranges. Write pnum and pcount first and the Config word last. Since the consumer is an external agent on coherent shared memory, use WRITE_ONCE() to stop the compiler from reordering the stores and smp_wmb() to make the parameter words globally visible before the Pending bit is set. | |
| Title | KVM: riscv: Fix NACL hfence entry update order | |
| First Time appeared |
Linux
Linux linux Kernel |
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| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Linux
Linux linux Kernel |
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| References |
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