irqchip/renesas-rzg2l: Fix loss of interrupt
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
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| Linux | Linux | unaffected |
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| Linux | Linux | affected |
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| Linux | Linux Kernel |
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| Linux | Linux Kernel |
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| Source | ID | Title |
|---|---|---|
Debian DLA |
DLA-4817-1 | linux-6.12 security update |
Debian DLA |
DLA-4841-1 | linux security update |
Debian DSA |
DSA-6528-1 | linux security update |
Ubuntu USN |
USN-9019-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-9020-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9022-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9023-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9024-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9025-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9026-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-9039-1 | Linux kernel (Azure CVM) vulnerabilities |
Ubuntu USN |
USN-9040-1 | Linux kernel (Low Latency NVIDIA) vulnerabilities |
Ubuntu USN |
USN-9066-1 | Linux kernel (HWE) vulnerabilities |
Ubuntu USN |
USN-9091-1 | Linux kernel (NVIDIA Tegra) vulnerabilities |
No CVSS v4.0
No CVSS v3.1
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.211% probability within 30 days)
Key SSVC decision points have not yet been added.
| Type | Values Removed | Values Added |
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| Weaknesses | CWE-727 |
| Type | Values Removed | Values Added |
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| Description | In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved. | |
| Title | irqchip/renesas-rzg2l: Fix loss of interrupt | |
| First Time appeared |
Linux
Linux linux Kernel |
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| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Linux
Linux linux Kernel |
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| References |
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