iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
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| Source | ID | Title |
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Ubuntu USN |
USN-8781-1 | Linux kernel (NVIDIA Tegra) vulnerabilities |
Ubuntu USN |
USN-8816-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8816-2 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8816-3 | Linux kernel (Oracle) vulnerabilities |
Ubuntu USN |
USN-8816-4 | Linux kernel (GKE) vulnerabilities |
Ubuntu USN |
USN-8888-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-8888-2 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-8917-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8918-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-9003-1 | Linux kernel (NVIDIA) vulnerabilities |
Ubuntu USN |
USN-9024-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9025-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-9026-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-9040-1 | Linux kernel (Low Latency NVIDIA) vulnerabilities |
Ubuntu USN |
USN-9043-1 | Linux kernel (NVIDIA) vulnerabilities |
Ubuntu USN |
USN-9066-1 | Linux kernel (HWE) vulnerabilities |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.196% probability within 30 days)
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| Weaknesses | CWE-367 | |
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| Description | In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry device_pasid_table_teardown() zeroes the 128-bit scalable-mode context entry with context_clear_entry() while the Present bit is still set. This creates a window where the hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behavior or spurious faults. The context-cache invalidation is issued only after the entry has been zeroed, and intel_pasid_free_table() then frees the PASID directory pages, so the IOMMU can keep walking a stale Present=1 entry that points at freed memory. While x86 provides strong write ordering, the compiler may reorder the two 64-bit writes to the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. Commit c1e4f1dccbe9d ("iommu/vt-d: Clear Present bit before tearing down context entry") fixed this exact pattern in domain_context_clear_one() and the copied-context path, but device_pasid_table_teardown() was not converted. Align it with the "Guidance to Software for Invalidations" in the VT-d spec, Section 6.5.3.3, using the same ownership handshake as the sibling fix: clear only the Present bit, flush it to the IOMMU, perform the context-cache invalidation, and only then zero the rest of the entry. | |
| Title | iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry | |
| First Time appeared |
Linux
Linux linux Kernel |
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| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Linux
Linux linux Kernel |
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| References |
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