PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
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Configuration 1 [-]
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| Source | ID | Title |
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Ubuntu USN |
USN-8566-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8568-1 | Linux kernel (OEM) vulnerabilities |
Ubuntu USN |
USN-8569-1 | Linux kernel (HWE) vulnerabilities |
Ubuntu USN |
USN-8593-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8603-1 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-8618-1 | Linux kernel vulnerabilities |
Ubuntu USN |
USN-8663-1 | Linux kernel (NVIDIA) vulnerabilities |
Ubuntu USN |
USN-8664-1 | Linux kernel (NVIDIA BaseOS) vulnerabilities |
Ubuntu USN |
USN-8728-1 | Linux kernel (GCP) vulnerabilities |
Ubuntu USN |
USN-8728-2 | Linux kernel (Azure) vulnerabilities |
Ubuntu USN |
USN-8728-3 | Linux kernel (Oracle) vulnerabilities |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.162% probability within 30 days)
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ssvc
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| Type | Values Removed | Values Added |
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| Weaknesses | CWE-20 CWE-399 |
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| Weaknesses | CWE-367 | |
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threat_severity
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cvssV3_1
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| Weaknesses | CWE-20 CWE-399 |
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| Description | In the Linux kernel, the following vulnerability has been resolved: PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on When PERST# is deasserted twice (assert -> deassert -> assert -> deassert), a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc (PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify() and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers on the controller core. The call chain that causes the timeout: pex_ep_event_pex_rst_deassert() pci_epc_deinit_notify() pci_epf_test_epc_deinit() pci_epf_test_clear_bar() pci_epc_clear_bar() dw_pcie_ep_clear_bar() __dw_pcie_ep_reset_bar() dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register reset_control_deassert(pcie->core_rst) <- Core powered on HERE The DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only accessible after the controller core is powered on via reset_control_deassert(pcie->core_rst). Accessing them before this point results in a CBB timeout because the hardware is not yet operational. Fix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to after reset_control_deassert(pcie->core_rst), ensuring the controller is fully powered on before any DBI register accesses occur. | |
| Title | PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on | |
| First Time appeared |
Linux
Linux linux Kernel |
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| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Linux
Linux linux Kernel |
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| References |
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