CVE-2026-29645

Published Apr 20, 2026 CVSS 3.1 · 7.5 High EPSS < 1% KEV · Not listed
Description
NEMU (OpenXiangShan/NEMU) before v2025.12.r2 contains an improper instruction-validation flaw in its RISC-V Vector (RVV) decoder. The decoder does not correctly validate the funct3 field when decoding vsetvli/vsetivli/vsetvl, allowing certain invalid OP-V instruction encodings to be misinterpreted and executed as vset* configuration instructions rather than raising an illegal-instruction exception. This can be exploited by providing crafted RISC-V binaries to cause incorrect trap behavior, architectural state corruption/divergence, and potential denial of service in systems that rely on NEMU for correct execution or sandboxing.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

No advisories available
History
Type Values Removed Values Added
First Time appeared Openxiangshan
Openxiangshan nemu
Vendors & Products Openxiangshan
Openxiangshan nemu
Type Values Removed Values Added
First Time appeared Xiangshan
Xiangshan nemu
CPEs cpe:2.3:a:xiangshan:nemu:2025.12:r1:*:*:*:*:*:*
Vendors & Products Xiangshan
Xiangshan nemu
Type Values Removed Values Added
Title Instruction Validation Flaw in NEMU's RISC-V Vector Decoder Allows Misinterpretation of Invalid Encodings
Weaknesses CWE-20
Type Values Removed Values Added
Weaknesses CWE-1287
CWE-131
Metrics cvssV3_1

{'score': 7.5, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H'}

ssvc

{'options': {'Automatable': 'yes', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Type Values Removed Values Added
Title Instruction Validation Flaw in NEMU's RISC-V Vector Decoder Allows Misinterpretation of Invalid Encodings
Weaknesses CWE-20
Type Values Removed Values Added
Description NEMU (OpenXiangShan/NEMU) before v2025.12.r2 contains an improper instruction-validation flaw in its RISC-V Vector (RVV) decoder. The decoder does not correctly validate the funct3 field when decoding vsetvli/vsetivli/vsetvl, allowing certain invalid OP-V instruction encodings to be misinterpreted and executed as vset* configuration instructions rather than raising an illegal-instruction exception. This can be exploited by providing crafted RISC-V binaries to cause incorrect trap behavior, architectural state corruption/divergence, and potential denial of service in systems that rely on NEMU for correct execution or sandboxing.
References
Weaknesses

Sources

Status
PUBLISHED
Assigner
mitre
Published
Updated
Apr 21, 2026, 7:51 PM
Reserved
Mar 4, 2026, 12:00 AM
Status
Analyzed
Published
Apr 20, 2026, 8:16 PM
Modified
Nov 11, 2026, 7:10 PM