Use after free of paging structures in EPT
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
| Vendor | Product | Default status | Versions | ||||||
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| Xen | Xen | unknown |
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No data.
| Vendor | Product | Versions | ||||||||
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| Xen | Xen |
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Vendor Workaround
There are no mitigations.
| Source | ID | Title |
|---|---|---|
Debian DLA |
DLA-4818-1 | xen security update |
Debian DSA |
DSA-6424-1 | xen security update |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.133% probability within 30 days)
| Type | Values Removed | Values Added |
|---|---|---|
| CPEs | cpe:2.3:o:xen:xen:*:*:*:*:*:*:x86:* |
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Xen
Xen xen |
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| Vendors & Products |
Xen
Xen xen |
| Type | Values Removed | Values Added |
|---|---|---|
| Weaknesses | CWE-367 | |
| Metrics |
cvssV3_1
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| Type | Values Removed | Values Added |
|---|---|---|
| References |
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| Type | Values Removed | Values Added |
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| Description | The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions. | |
| Title | Use after free of paging structures in EPT | |
| References |
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