Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
| Vendor | Product | Default status | Versions | ||||||
|---|---|---|---|---|---|---|---|---|---|
| AMD | Versal™ Adaptive SoC Devices | affected |
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| AMD | Versal™ RF Series | affected |
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| AMD | Versal™ AI Edge Series | affected |
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| AMD | Versal™ Prime Series | affected |
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| AMD | Versal™ Premium Series | affected |
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| AMD | Versal™ AI Core Series | affected |
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| AMD | Versal™ HBM Series | affected |
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| AMD | Alveo™ V80 Compute Accelerator | affected |
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No data.
No data.
| Vendor | Product | Versions |
|---|---|---|
| Amd | Alveo | — |
| Amd | Versal | — |
| Arm | Cortex-a | — |
| Arm | Trusted Firmware-a | — |
No CVSS v3.1
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.133% probability within 30 days)
| Type | Values Removed | Values Added |
|---|---|---|
| Description | The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state. | The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state. |
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Amd
Amd alveo Amd versal Arm Arm cortex-a Arm trusted Firmware-a |
|
| Vendors & Products |
Amd
Amd alveo Amd versal Arm Arm cortex-a Arm trusted Firmware-a |
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
ssvc
|
| Type | Values Removed | Values Added |
|---|---|---|
| Description | The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state. | |
| Weaknesses | CWE-1284 | |
| References |
| |
| Metrics |
cvssV4_0
|