CVE-2025-51679

RTL and Netlist Mismatch in openRISC OR1200 Core Causes Unpredictable Behavior

Published Aug 26, 2026 CVSS 3.1 · 9.1 Critical EPSS < 1% KEV · Not listed
Description
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

No advisories available
History
Type Values Removed Values Added
Title RTL and Netlist Mismatch in openRISC OR1200 Core Causes Unpredictable Behavior
Type Values Removed Values Added
Title RTL and Netlist Mismatch Causing Unexpected Hardware Behavior
Weaknesses CWE-710
Type Values Removed Values Added
Weaknesses CWE-1281
Metrics cvssV3_1

{'score': 9.1, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H'}

ssvc

{'options': {'Automatable': 'yes', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Type Values Removed Values Added
First Time appeared Openrisc
Openrisc or1200
Vendors & Products Openrisc
Openrisc or1200
Type Values Removed Values Added
Title RTL and Netlist Mismatch Causing Unexpected Hardware Behavior
Weaknesses CWE-710
Type Values Removed Values Added
Description An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.
References
Weaknesses

Sources

Status
PUBLISHED
Assigner
mitre
Published
Updated
Aug 27, 2026, 6:06 PM
Reserved
Jun 16, 2025, 12:00 AM
Status
Deferred
Published
Aug 26, 2026, 9:16 PM
Modified
Oct 26, 2026, 9:10 PM