CVE-2025-51677

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{"affected": [{"affectedData": [{"product": "n/a", "vendor": "n/a", "versions": [{"status": "affected", "version": "n/a"}]}], "source": "cve@mitre.org"}], "cveTags": [], "descriptions": [{"lang": "en", "value": "An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior."}, {"lang": "es", "value": "Se descubri\u00f3 un problema en openRISC OR1200 commit 83ac6b. Una discrepancia de salida entre el RTL y la netlist del puerto de salida de la CPU or1200 puede llevar a un comportamiento inesperado."}], "id": "CVE-2025-51677", "lastModified": "2026-10-13T09:10:00.323", "metrics": {"cvssMetricV31": [{"cvssData": {"attackComplexity": "LOW", "attackVector": "NETWORK", "availabilityImpact": "HIGH", "baseScore": 9.1, "baseSeverity": "CRITICAL", "confidentialityImpact": "NONE", "integrityImpact": "HIGH", "privilegesRequired": "NONE", "scope": "UNCHANGED", "userInteraction": "NONE", "vectorString": "CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:H/A:H", "version": "3.1"}, "exploitabilityScore": 3.9, "impactScore": 5.2, "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "type": "Secondary"}], "ssvcV203": [{"source": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "ssvcData": {"id": "CVE-2025-51677", "options": [{"exploitation": "none"}, {"automatable": "yes"}, {"technicalImpact": "partial"}], "role": "CISA Coordinator", "timestamp": "2026-07-20T18:12:04.677167Z", "version": "2.0.3"}}]}, "published": "2026-07-17T20:17:13.763", "references": [{"source": "cve@mitre.org", "url": "https://github.com/openrisc/mor1kx/issues/160#issuecomment-2585618940"}, {"source": "cve@mitre.org", "url": "https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.html"}, {"source": "cve@mitre.org", "url": "https://www.arxiv.org/abs/2504.18812"}], "sourceIdentifier": "cve@mitre.org", "vulnStatus": "Deferred", "weaknesses": [{"description": [{"lang": "en", "value": "CWE-116"}], "source": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "type": "Secondary"}]}

{}

{"affected": [{"configurations": [{"platform": null, "status": "affected", "versions": {"scheme": "generic", "value": "83ac6b"}}], "enrichment": {"confidence": 90.0, "confidence_source": "inferred", "scores": [{"score": 90.0, "source": "inferred"}, {"score": 100.0, "source": "matching"}]}, "original": {"product": "n/a", "source": "cna", "vendor": "n/a"}, "product": "or1200", "vendor": "openrisc"}], "created": "2026-07-17T22:00:04.378869+00:00", "title": "Unpredictable CPU Output from RTL/Netlist Mismatch in openRISC OR1200", "updated": "2026-07-31T01:15:18.427958+00:00", "vendors": ["openrisc", "openrisc$PRODUCT$or1200"]}