CVE-2025-45006

Published Jul 1, 2025 CVSS 3.1 · 9.1 Critical EPSS < 1% KEV · Not listed
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

Source ID Title
EUVD EUVD EUVD-2025-19672 Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
History
Type Values Removed Values Added
Weaknesses CWE-266
Metrics cvssV3_1

{'score': 9.1, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H'}

ssvc

{'options': {'Automatable': 'yes', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Type Values Removed Values Added
Description Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
References

Subscriptions

No data.

Weaknesses

Sources

Status
PUBLISHED
Assigner
mitre
Published
Updated
Jul 2, 2025, 1:58 PM
Reserved
Apr 22, 2025, 12:00 AM
Status
Deferred
Published
Jul 1, 2025, 8:15 PM
Modified
Jun 17, 2026, 9:25 AM