Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
| Vendor | Product | Default status | Versions | ||||||
|---|---|---|---|---|---|---|---|---|---|
| Arm | Neoverse-N2 | unaffected |
|
||||||
| Arm | Neoverse-V3AE | unaffected |
|
||||||
| Arm | Neoverse-V3 | unaffected |
|
||||||
| Arm | Neoverse-V2 | unaffected |
|
||||||
| Arm | Cortex-X925 | unaffected |
|
||||||
| Arm | Cortex-X4 | unaffected |
|
||||||
| Arm | Cortex-X3 | unaffected |
|
||||||
| Arm | Cortex-X2 | unaffected |
|
||||||
| Arm | Cortex-A710 | unaffected |
|
||||||
| Arm | C1-Premium | unaffected |
|
||||||
| Arm | C1-Ultra | unaffected |
|
Configuration 1 [-]
| AND |
|
Configuration 2 [-]
| AND |
|
Configuration 3 [-]
| AND |
|
Configuration 4 [-]
| AND |
|
Configuration 5 [-]
| AND |
|
Configuration 6 [-]
| AND |
|
Configuration 7 [-]
| AND |
|
Configuration 8 [-]
| AND |
|
Configuration 9 [-]
| AND |
|
Configuration 10 [-]
| AND |
|
Configuration 11 [-]
| AND |
|
No data.
| Vendor | Product | Versions |
|---|---|---|
| Arm | C1-premium | — |
| Arm | C1-ultra | — |
| Arm | Cortex-a710 | — |
| Arm | Cortex-x2 | — |
| Arm | Cortex-x3 | — |
| Arm | Cortex-x4 | — |
| Arm | Cortex-x925 | — |
| Arm | Neoverse-v2 | — |
| Arm | Neoverse-v3 | — |
| Arm | Neoverse-v3ae | — |
| Arm | Neoverse N2 | — |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.167% probability within 30 days)
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Arm c1-premium Firmware
Arm c1-ultra Firmware Arm cortex-a710 Firmware Arm cortex-x2 Firmware Arm cortex-x3 Firmware Arm cortex-x4 Firmware Arm cortex-x925 Firmware Arm neoverse-n2 Arm neoverse-n2 Firmware Arm neoverse-v2 Firmware Arm neoverse-v3 Firmware Arm neoverse-v3ae Firmware |
|
| CPEs | cpe:2.3:h:arm:c1-premium:-:*:*:*:*:*:*:* cpe:2.3:h:arm:c1-ultra:-:*:*:*:*:*:*:* cpe:2.3:h:arm:cortex-a710:-:*:*:*:*:*:*:* cpe:2.3:h:arm:cortex-x2:-:*:*:*:*:*:*:* cpe:2.3:h:arm:cortex-x3:-:*:*:*:*:*:*:* cpe:2.3:h:arm:cortex-x4:-:*:*:*:*:*:*:* cpe:2.3:h:arm:cortex-x925:-:*:*:*:*:*:*:* cpe:2.3:h:arm:neoverse-n2:-:*:*:*:*:*:*:* cpe:2.3:h:arm:neoverse-v2:-:*:*:*:*:*:*:* cpe:2.3:h:arm:neoverse-v3:-:*:*:*:*:*:*:* cpe:2.3:h:arm:neoverse-v3ae:-:*:*:*:*:*:*:* cpe:2.3:o:arm:c1-premium_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:c1-ultra_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:cortex-a710_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:cortex-x2_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:cortex-x3_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:cortex-x4_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:cortex-x925_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:neoverse-n2_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:neoverse-v2_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:neoverse-v3_firmware:-:*:*:*:*:*:*:* cpe:2.3:o:arm:neoverse-v3ae_firmware:-:*:*:*:*:*:*:* |
|
| Vendors & Products |
Arm c1-premium Firmware
Arm c1-ultra Firmware Arm cortex-a710 Firmware Arm cortex-x2 Firmware Arm cortex-x3 Firmware Arm cortex-x4 Firmware Arm cortex-x925 Firmware Arm neoverse-n2 Arm neoverse-n2 Firmware Arm neoverse-v2 Firmware Arm neoverse-v3 Firmware Arm neoverse-v3ae Firmware |
| Type | Values Removed | Values Added |
|---|---|---|
| References |
| |
| Metrics |
cvssV3_1
|
cvssV3_1
|
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
cvssV3_1
|
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Arm
Arm c1-premium Arm c1-ultra Arm cortex-a710 Arm cortex-x2 Arm cortex-x3 Arm cortex-x4 Arm cortex-x925 Arm neoverse-v2 Arm neoverse-v3 Arm neoverse-v3ae Arm neoverse N2 |
|
| Vendors & Products |
Arm
Arm c1-premium Arm c1-ultra Arm cortex-a710 Arm cortex-x2 Arm cortex-x3 Arm cortex-x4 Arm cortex-x925 Arm neoverse-v2 Arm neoverse-v3 Arm neoverse-v3ae Arm neoverse N2 |
| Type | Values Removed | Values Added |
|---|---|---|
| Description | In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI. | |
| Weaknesses | CWE-226 | |
| References |
|