CVE-2025-0647

Published Jan 14, 2026 CVSS 3.1 · 7.9 High EPSS < 1% KEV · Not listed
Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

No advisories available
History
Type Values Removed Values Added
First Time appeared Arm c1-premium Firmware
Arm c1-ultra Firmware
Arm cortex-a710 Firmware
Arm cortex-x2 Firmware
Arm cortex-x3 Firmware
Arm cortex-x4 Firmware
Arm cortex-x925 Firmware
Arm neoverse-n2
Arm neoverse-n2 Firmware
Arm neoverse-v2 Firmware
Arm neoverse-v3 Firmware
Arm neoverse-v3ae Firmware
CPEs cpe:2.3:h:arm:c1-premium:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:c1-ultra:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:cortex-a710:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:cortex-x2:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:cortex-x3:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:cortex-x4:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:cortex-x925:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:neoverse-n2:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:neoverse-v2:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:neoverse-v3:-:*:*:*:*:*:*:*
cpe:2.3:h:arm:neoverse-v3ae:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:c1-premium_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:c1-ultra_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:cortex-a710_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:cortex-x2_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:cortex-x3_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:cortex-x4_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:cortex-x925_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:neoverse-n2_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:neoverse-v2_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:neoverse-v3_firmware:-:*:*:*:*:*:*:*
cpe:2.3:o:arm:neoverse-v3ae_firmware:-:*:*:*:*:*:*:*
Vendors & Products Arm c1-premium Firmware
Arm c1-ultra Firmware
Arm cortex-a710 Firmware
Arm cortex-x2 Firmware
Arm cortex-x3 Firmware
Arm cortex-x4 Firmware
Arm cortex-x925 Firmware
Arm neoverse-n2
Arm neoverse-n2 Firmware
Arm neoverse-v2 Firmware
Arm neoverse-v3 Firmware
Arm neoverse-v3ae Firmware
Type Values Removed Values Added
References
Metrics cvssV3_1

{'score': 5.4, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:L/I:L/A:N'}

ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

cvssV3_1

{'score': 7.9, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N'}

ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'total'}, 'version': '2.0.3'}

Type Values Removed Values Added
Metrics cvssV3_1

{'score': 5.4, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:L/I:L/A:N'}

ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Type Values Removed Values Added
First Time appeared Arm
Arm c1-premium
Arm c1-ultra
Arm cortex-a710
Arm cortex-x2
Arm cortex-x3
Arm cortex-x4
Arm cortex-x925
Arm neoverse-v2
Arm neoverse-v3
Arm neoverse-v3ae
Arm neoverse N2
Vendors & Products Arm
Arm c1-premium
Arm c1-ultra
Arm cortex-a710
Arm cortex-x2
Arm cortex-x3
Arm cortex-x4
Arm cortex-x925
Arm neoverse-v2
Arm neoverse-v3
Arm neoverse-v3ae
Arm neoverse N2
Type Values Removed Values Added
Description In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Weaknesses CWE-226
References