CVE-2025-0036

Published Jun 9, 2025 CVSS 3.1 · 3.2 Low EPSS < 1% KEV · Not listed
Description
In AMD Versal Adaptive SoC devices, the incorrect configuration of the SSS during runtime (post-boot) cryptographic operations could cause data to be incorrectly written to and read from invalid locations as well as returning incorrect cryptographic data.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

Source ID Title
EUVD EUVD EUVD-2025-17610 In AMD Versal Adaptive SoC devices, the incorrect configuration of the SSS during runtime (post-boot) cryptographic operations could cause data to be incorrectly written to and read from invalid locations as well as returning incorrect cryptographic data.
History
Type Values Removed Values Added
Metrics epss

{'score': 0.00011}

epss

{'score': 0.00013}

Type Values Removed Values Added
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Type Values Removed Values Added
Description In AMD Versal Adaptive SoC devices, the incorrect configuration of the SSS during runtime (post-boot) cryptographic operations could cause data to be incorrectly written to and read from invalid locations as well as returning incorrect cryptographic data.
Weaknesses CWE-497
CWE-682
CWE-772
CWE-940
CWE-941
References
Metrics cvssV3_1

{'score': 3.2, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:L/UI:R/S:C/C:L/I:N/A:N'}

Subscriptions

No data.

Sources

Status
PUBLISHED
Assigner
AMD
Published
Updated
Jun 30, 2025, 2:48 PM
Reserved
Nov 21, 2024, 4:18 PM
Status
Deferred
Published
Jun 10, 2025, 12:15 AM
Modified
Jun 17, 2026, 8:25 AM