CVE-2024-24853

Published Aug 14, 2024 CVSS 4.0 · 7.3 High EPSS < 1% KEV · Not listed
Description
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

Source ID Title
EUVD EUVD EUVD-2024-22216 Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Ubuntu USN Ubuntu USN USN-6967-1 Intel Microcode vulnerabilities
History
Type Values Removed Values Added
First Time appeared Intel
Intel processor
CPEs cpe:2.3:a:intel:processor:*:*:*:*:*:*:*:*
Vendors & Products Intel
Intel processor
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'total'}, 'version': '2.0.3'}

Type Values Removed Values Added
Description Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Weaknesses CWE-696
References
Metrics cvssV3_1

{'score': 7.2, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H'}

cvssV4_0

{'score': 7.3, 'vector': 'CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H'}

Weaknesses

Sources

Status
PUBLISHED
Assigner
intel
Published
Updated
Aug 16, 2024, 4:01 AM
Reserved
Feb 8, 2024, 4:00 AM
Status
Deferred
Published
Aug 14, 2024, 2:15 PM
Modified
Jun 17, 2026, 7:15 AM