drm/amd/display: Do not set DRR on pipe Commit
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
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| Linux | Linux | unaffected |
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| Linux | Linux | affected |
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Configuration 1 [-]
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No data.
| Vendor | Product | Versions |
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| Linux | Linux Kernel | — |
| Source | ID | Title |
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EUVD |
EUVD-2025-13225 | In the Linux kernel, the following vulnerability has been resolved: drm/amd/display: Do not set DRR on pipe Commit [WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.199% probability within 30 days)
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ssvc
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| Weaknesses | NVD-CWE-noinfo | |
| CPEs | cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:* cpe:2.3:o:linux:linux_kernel:6.3:rc1:*:*:*:*:*:* cpe:2.3:o:linux:linux_kernel:6.3:rc2:*:*:*:*:*:* |
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threat_severity
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cvssV3_1
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| Type | Values Removed | Values Added |
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| Description | In the Linux kernel, the following vulnerability has been resolved: drm/amd/display: Do not set DRR on pipe Commit [WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. | |
| Title | drm/amd/display: Do not set DRR on pipe Commit | |
| References |
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