CVE-2023-34326

x86/AMD: missing IOMMU TLB flushing

Published Jan 5, 2024 CVSS 3.1 · 7.8 High EPSS < 1% KEV · Not listed
Description
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.

Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.

Remediation

Vendor Workaround

Not passing through physical devices to guests will avoid the vulnerability.

Tracking

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Advisories

Source ID Title
EUVD EUVD EUVD-2023-38407 The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
History
Type Values Removed Values Added
Weaknesses CWE-672
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'total'}, 'version': '2.0.3'}

Weaknesses

Sources

Status
PUBLISHED
Assigner
XEN
Published
Updated
Nov 4, 2025, 7:16 PM
Reserved
Jun 1, 2023, 10:44 AM
Status
Modified
Published
Jan 5, 2024, 5:15 PM
Modified
Jun 17, 2026, 6:03 AM