x86/AMD: missing IOMMU TLB flushing
Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).
| Vendor | Product | Default status | Versions | ||||||
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| Xen | Xen | unknown |
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No data.
No data available yet.
Vendor Workaround
Not passing through physical devices to guests will avoid the vulnerability.
| Source | ID | Title |
|---|---|---|
EUVD |
EUVD-2023-38407 | The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions. |
No CVSS v4.0
No CVSS v3.0
No CVSS v2
This CVE is not in the KEV list.
Exploit prediction score: < 1% (0.275% probability within 30 days)
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| References |
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| Type | Values Removed | Values Added |
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| Weaknesses | CWE-672 | |
| Metrics |
ssvc
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