CVE-2020-0574

Published Mar 12, 2020 CVSS 3.1 · 5.9 Medium EPSS < 1% KEV · Not listed
Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

Remediation

No solution or workaround provided in the CVE record

Tracking

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Advisories

Source ID Title
EUVD EUVD EUVD-2020-2072 Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
History

No history.

Weaknesses

Sources

Status
PUBLISHED
Assigner
intel
Published
Updated
Aug 4, 2024, 6:02 AM
Reserved
Oct 28, 2019, 12:00 AM
Status
Modified
Published
Mar 12, 2020, 9:15 PM
Modified
Jun 17, 2026, 2:46 AM