Physical Access Enables Reading and Writing of Debug Registers on AMD Ryzen Processors

Improper access control between the Joint Test Action Group (JTAG) and Advanced Extensible Interface (AXI) could allow an attacker with physical access to read or overwrite the contents of cross-chip debug (XCD) registers potentially resulting in loss of data integrity or confidentiality.

TEE SOC Driver Parameter Sanitization Flaw in AMD Instinct GPUs Allows Malformed Command

Insufficient parameter sanitization in TEE SOC Driver could allow an attacker to issue a malformed DRV_SOC_CMD_ID_SRIOV_COPY_VF_CHIPLET_REGS to write invalid data to a remote Die, potentially resulting in unexpected behavior.

Improper Signature Verification in Radeon RGB Tool Enables Privilege Escalation

Improper verification of cryptographic signature in the Radeon RGB tool could allow a malicious file placed in the installation directory to be run with elevated privileges potentially leading to arbitrary code execution.

Incorrect Shared Memory Mapping via Malformed TEE SOC Command

Insufficient parameter sanitization in TEE SOC Driver could allow an attacker to issue a malformed DRV_SOC_CMD_ID_SRIOV_CHECK_TA_COMPAT to cause incorrect shared memory mapping, potentially resulting in unexpected behavior.

Unchecked return value in AMD PMF enables arbitrary memory write

An unchecked return value within the AMD Platform Management Framework (PMF) could allow an attacker to write to an arbitrary memory address resulting in denial of service or arbitrary code execution.

Out‑of‑Bounds Write in AMD GPU Diagnostic IOCTL Enables Local Privilege Escalation

Out of bounds write in AMD AMDGV_CMD_GET_DIAG_DATA ioctl handler could allow a local user to escalate privileges via remote code execution.

Guest VM Privilege Escalation: Unauthorized GPU Register Access Causing Host Reboot

Improper isolation of GPU HW register space could allow a privileged attacker in malicious Guest Virtual Machine (VM) to perform unauthorized access to specific victim range of GPU MMIO register space, potentially causing the host OS to reboot and creating a Denial of Service (DOS) condition.

Improper cleanup of GPU shared register resources enabling cross‑VM data leakage

Improper cleanup of shared register resources in GPU firmware could allow an admin-privileged attacker from a Guest Virtual machine (VM) to access these shared resources from another Guest VM, potentially resulting in the loss of confidentiality, integrity, or availability.

Out‑of‑Bounds Read in Power‑Management Firmware Enables Partial Confidentiality and Availability Loss

An out-of-bounds read in power management firmware by a malicious local attacker with low privileges could potentially lead to a partial loss of confidentiality and availability.

Arbitrary Code Execution via Buffer Overflow in AMD Secure Processor

Improper restriction of operations within the bounds of a memory buffer in the AMD secure processer (ASP) could allow an attacker to read or write to protected memory potentially resulting in arbitrary code execution.

Unauthorized Access via Improper VCN‑JPEG Register Isolation in AMD GPU Systems

Improper isolation of VCN-JPEG HW register space could allow a malicious Guest Virtual Machine (VM) or a process to perform unauthorized access to the register space of the JPEG cores assigned a victim VM/process, potentially gaining arbitrary read/write access to the victim VM/process data.

Race Condition in AMD Instinct GPU Virtualization Driver Causes Heap‑Based Buffer Overflow and Denial of Service

A race condition in the MxGPU-Virtualization driver’s ioctl path caused by concurrent unsynchronized access to the global variable amdgv_cmd in an unlocked ioctl handler could be exploited by an attacker to trigger a heap-based buffer overflow, potentially resulting in denial-of-service within the vulnerable system context.

Out‑of‑Bounds Read in AMD Instinct Remote Management Firmware

An out of bounds read in the remote management firmware could allow a privileged attacker read a limited section of memory outside of established bounds potentially resulting in loss of confidentiality or availability.

Unrestricted IP Binding Allows Remote Unauthorized GPU Configuration Changes on AMD Instinct GPUs

Unrestricted IP address binding in the AMD Device Metrics Exporter (ROCm ecosystem) could allow a remote attacker to perform unauthorized changes to the GPU configuration, potentially resulting in loss of availability

Insufficient checking of memory buffer in AMD Secure Processor (ASP) Secure OS may allow an attacker with a malicious trusted application to read/write to the ASP Secure OS kernel virtual address space, potentially resulting in privilege escalation.

Speculative Execution Bypass via Improper LFENCE Enforcement Leading to Potential Data Disclosure

Improper enforcement of the LFENCE serialization property may allow an attacker to bypass speculation barriers and potentially disclose sensitive information, potentially resulting in loss of confidentiality.

Heap-based Buffer Overflow in AMD Pensando DPU Ionic Cloud Driver Allowing Privilege Escalation

A heap-based buffer overflow in the ionic cloud driver for VMware ESXi could allow an attacker to achieve privilege escalation, potentially resulting in arbitrary code execution.

Heap Overflow in VMware ESXi Ionic Cloud Driver Enables Privilege Escalation

A heap-based buffer overflow in the ionic cloud driver for VMware ESXi could allow an attacker to achieve privilege escalation, potentially resulting in arbitrary code execution.

Untrusted Pointer Dereference in VMware ESXi Ionic Cloud Driver Enables Unprivileged VM Memory Leakage

An untrusted pointer dereference in the ionic cloud driver for VMWare ESXi could allow an attacker with an unprivileged VM to read kernel memory or co-located guest VM memory, potentially resulting in loss of confidentiality or availability.

Insufficient Lock‑Bit Protection Enabling Unauthorized MMIO Routing Modification

Missing lock bit protection for NBIO registers could allow a local admin-privileged attacker to modify MMIO routing configurations, potentially resulting in loss of SEV-SNP guest integrity.